1. Field of the Invention
The present invention relates to semiconductor fabrication, and more particularly to a method for forming ohmic contacts for thin film transistors (TFTs).
2. Description of the Related Art
Thin film transistors (TFTs) may be employed in a plurality of different applications. In one instance, TFTs are employed in active matrix displays for the purpose of pixel switching. There are a variety of TFT structures described in the prior art. Referring to FIGS. 1-4, four examples (in cross-section) are shown of TFT structures including two top gate designs (FIGS. 1 and 2) and two bottom gate designs (FIGS. 3 and 4).
Each of FIGS. 1-4 include commonly labeled elements which function in a same manner. Each structure includes a source S, a drain D, and a gate G. All structures are formed on a substrate 10 and include insulation layers 11.
FIG. 1 shows a structure similar to that found in silicon CMOS technology. This top gate TFT is common in polysilicon products where the gate. G is used as a shadow mask during S/D ion implantation. Laser irradiation is typically employed in this process flow, both for recrystallization of polysilicon 14 and for dopant activation in contact vias. A channel 15 is formed below gate G between source S and drain D. The TFT structure of FIG. 1 has S/D contacts 16 directly connected to the accumulated electron channel 15, i.e. the S/D and the channel are coplanar.
FIGS. 2 through 4 are employed when a semiconducting layer 22 (e.g., amorphous silicon (a-Si)) in a channel region 20 (under the gate G in FIG. 2 and over the gate G in FIGS. 3 and 4) of the TFT is of low mobility and essentially undoped, e.g. a-Si. Since the electron mobility is substantially larger than the hole mobility in a-Si, the TFTs have heavily n-type (n+) D/S contact regions 24. FIG. 2 shows a simple top gate structure where S metal and D metal are made ohmic either by encapsulation with n+ silicon or by a surface plasma doping treatment to form layer 24.
FIGS. 3 and 4 show two bottom gate TFT structures, whose channels and S/D contacts are on opposite sides of the a-Si layer; for this reasons they are known as inverted staggered type TFTs. FIG. 3 shows what is known as a channel passivated or an etch-stopper type TFT, while FIG. 4 shows a back-channel etch (BCE)structure. These structures normally employ a plasma enhanced chemical vapor deposited (PECVD) n+ layer 24 between metal employed for source S and drain D and a-Si layer 22. The TFT structures of FIGS. 3 and 4 differ, in that, the a-Si channel region 20 of FIG. 3 is protected from attack during the n+ etching step for layer 24 by an additional patterned layer of nitride known as an etch stop layer 23.
In the TFT structure of FIG. 4, any n+ over-etch removes a portion of the active channel a-Si layer 22. The inverted staggered structure (FIG. 3) needs additional PECVD and photoexposure steps thereby making it more costly, but the TFT performance is better than with the BCE TFT (FIG. 4). One reason for this is that the a-Si layer 22 in the BCE structure should be made thicker to allow for the n+ overetch, and this increases the parasitic resistance at the S/D ohmic contacts, i.e., the contacts formed by layer 24. Generally the BCE-type TFTs have shorter channel lengths to help compensate for lower mobility. This in turn places additional burden on the contacts since a greater portion of the total potential across the TFT is dropped across the D/S contacts when the channel is shorter.
For each of the above-mentioned TFTs, there exist tradeoffs in complexity, cost and performance. Many of these tradeoffs stem from a common problemxe2x80x94how to form ohmic S/D contacts which are needed for hole blocking and efficient electron injection. The etch-stopper or channel passivated TFT accepts greater process complexity for good a-Si channel performance, while the BCE process trades channel performance for simplicity.
Referring again to FIG. 2, in the top gate TFT, n+ deposition for layer 24 may be used, but this requires two S/D photosteps since the n+ layer 24 must completely clad the S/D metal, including any tapered edge, to be effective. Plasma-doping may be employed, where, for example, a thin layer of P atoms are deposited on the surface of the patterned S/D metal thereby doping the subsequently deposited a-Si layer 22 adjacent to the contacts. This method is the subject of U.S. Pat. No. 5,061,648 where the S/D material is a transparent conductive oxide (TCO), e.g. ITO. U.S. Pat. No. 5,061,648 patterns S/D material and introduces dopant species onto/into the S/D surface in separate steps. Disadvantages of this method, besides the limitation of using TCO for the S/D, are that the plasma doping process window is necessarily narrow to avoid doping a gate insulator adjacent to the channel region, and the doped layer properties cannot be accurately controlled.
In conventional structures such as those shown in FIGS. 2-4, layer 24 is highly-doped and, is responsible for the formation of ohmic contacts. Layer 24 is typically formed by performing one of the following steps: i) depositing an n+ plasma enhanced chemical vapor deposition (PECVD) layer 24, ii) plasma doping exposure to form layer 24, or iii) ion implantation to form layer 24.
Therefore, a need exists for a method for simplifying the formation of ohmic contacts for thin film transistors. A further need exists for a method for forming ohmic contacts without the need for an intermediate fabrication step, for example, ion implantation, plasma doping or n+ plasma enhanced chemical vapor deposition.
A method for forming ohmic contacts for semiconductor devices, in accordance with the present invention, includes forming a layer containing metal which includes dopants integrally formed therein. The layer containing metal is patterned to form components for a semiconductor device, and a semiconductor layer is deposited for contacting the layer containing metal. The semiconductor device is annealed to outdiffuse dopants from the layer containing metal into the semiconductor layer to form ohmic contacts therebetween.
Another method for forming ohmic contacts for thin film transistors; in accordance with the invention, includes the steps of patterning a gate conductor on a substrate, forming an insulation layer over the gate structure, depositing a layer containing silicon, forming a layer containing metal which includes dopants integrally formed therein in contact with the layer containing silicon, patterning the layer containing metal to form a gap over the gate conductor, the layer containing metal forming a source and drain for the thin film transistor and annealing the thin film transistor to outdiffuse dopants from the layer containing metal into the layer containing silicon to form ohmic contacts therebetween.
Yet another method for forming ohmic contacts for thin film transistors, in accordance with the present invention includes steps of depositing an insulation layer on a substrate, forming a layer containing metal which includes dopants integrally formed therein over the insulation layer, patterning the layer containing metal to form a source and a drain for the thin film transistor having a gap therebetween, depositing a layer containing silicon in contact with the insulation layer in the gap and in contact with the layer containing metal, annealing the thin film transistor to outdiffuse dopants from the layer containing metal into the layer containing silicon to form ohmic contacts therebetween, patterning a gate dielectric over the gap and forming a gate conductor over the gap.
In other methods, the step of patterning the layer containing metal to form components for a semiconductor device may include the step of patterning the layer containing metal to form source and drain metallizations for a thin film transistor. The layer containing metal may include at least one of cobalt, molybdenum, titanium, chromium and nickel. The layer containing metal may include between about 1 to about 30 atomic percent of the dopants. The layer containing metal may include at least one of phosphorous, antimony, arsenic and boron integrally formed therein.
The step of depositing a semiconductor layer may include the step of depositing a layer of one of amorphous silicon and polycrystalline silicon. The step of annealing the semiconductor device may include the step of annealing the semiconductor device at temperatures between about 300xc2x0 C. and about 400xc2x0 C. for between about 10 and about 30 minutes. The step of forming a layer containing metal may include the steps of forming a metal-dopant layer for contacting the layer containing silicon, and forming a conductive layer which contacts the metal-dopant layer. The layer containing metal may include a transparent conductive oxide (TCO). The step of forming a layer containing metal may include the step of forming the layer containing metal by one of co-sputtering, sputtering from a composite target, evaporation, thermal chemical vapor deposition and chemical solution deposition. The step of depositing a layer containing silicon may include the step of depositing a layer of one of amorphous silicon and polycrystalline silicon.